1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an LCD device and a method of fabricating the same.
2. Discussion of the Related Art
Generally, an LCD device uses the optical anisotropy and the polarization properties of liquid crystal molecules to display images. Liquid crystal molecules have a defined orientation and alignment order resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules may be controlled by applying an electric field to the liquid crystal molecules. As the intensity of the electric field is changed, the alignment of the liquid crystal molecules also changes. Because incident light through liquid crystal is refracted based on an orientation of the liquid crystal molecules, due to the optical anisotropy of the aligned liquid crystal molecules, intensity of the incident light may be controlled and images may be displayed.
Active matrix LCD (AM-LCD) devices are commonly used LCD devices. AM-LCD devices have thin film transistors (TFTs) disposed in a matrix and pixel electrodes connected to the TFTs. AM-LCD devices have been developed because of their high resolution and superiority in displaying moving images.
FIG. 1 is a schematic perspective view of a liquid crystal display device according to the related art. In FIG. 1, an LCD device includes a first substrate 81, a second substrate 11 facing the first substrate 81 and a liquid crystal layer 70 interposed therebetween.
A color filter layer 89 including red, green and blue sub-color filters 89a, 89b and 89c is formed on an inner surface of the first substrate 81, a black matrix 85 is formed between adjacent red, green and blue sub-color filters 89a, 89b and 89c, and a transparent common electrode 92 on the color filter layer 89 and the black matrix 85.
A pixel electrode 65, a switching element “Tr” and array lines are formed on the second substrate 11. The switching element “Tr,” for example, is a thin film transistor (TFT) disposed in a matrix arrangement and connected to a gate line 15 and a data line 40 that cross each other. A pixel region P is defined at a crossing portion of the gate line 15 and the data line 40. The pixel electrode 65 may be made of a transparent conductive material disposed in the pixel region “P.”
Substantially, the black matrix 85 may correspond to a non-pixel region (not show).
A voltage may be applied to the liquid crystal layer 70 to impart an electro-optical effect to the liquid crystal layer 70. This electro-optical effect drives the LCD device. Because the liquid crystal layer 70 is made of a material having dielectric anisotropy and spontaneous polarization, a dipole is formed in the liquid crystal layer 70 due to the spontaneous polarization that occurs when a voltage is applied. Thus, an alignment direction of liquid crystal molecules is changed according to a direction of an electric field resulting from the applied voltage. Optical properties of the LCD device depend on the alignment order of liquid crystal molecules. The alignment order causes an electrical light modulation. The LCD device displays images by shielding or transmitting light using the electrical light modulation.
First and second polarizers (not shown) transmit light parallel to polarizer axes and may be disposed on outer sides of the first and second substrates 81 and 11, respectively. A backlight unit (not shown) is used as a light source and may be disposed under one of the polarizers.
FIG. 2 is a schematic plan view showing an array substrate for an LCD device according to the related art. FIG. 3 is a schematic cross-sectional view taken along a line III-III of FIG. 2.
In FIGS. 2 and 3, a gate line 15 and a data line 40 cross each other to define a pixel region “P” and a switching element TFT “Tr” is disposed at a crossing of the gate line 15 and the data line 40. A scan signal and an image signal are supplied to the gate line 15 and the data line 40, respectively, from an external circuit (not shown). The TFT “Tr” is connected to the gate line 15, the data line 40, and a pixel electrode 65 in the pixel region “P.”
The TFT “Tr” includes a gate electrode 18, a semiconductor layer 35, and source and drain electrodes 43 and 46. The semiconductor layer 35 includes an active layer 35a and an ohmic contact layer 35b. The gate electrode 18 is connected to the gate line 15. The source and drain electrodes 43 and 46 are formed to overlap the gate electrode 18 and are spaced apart from each other. Part of the semiconductor layer 35 occupies a space between the source and drain electrodes 43 and 46. The source electrode 43 is connected to the data line 40 and the drain electrode 46 is connected to the pixel electrode 65.
The gate line 15 may be classified as a (n−1)th gate line. Thus, a nth gate line is adjacent the (n−1)th gate line. The (n−1)th gate line has a width W1. A nth storage capacitor “Cst” (nth Cst) includes a first storage electrode 20 occupying a portion of the (n−1)th gate line 15 and a second storage electrode 66 extended from the pixel electrode 65 to overlap with the first storage electrode 20.
The cross-sectional structure of the array substrate of the related art will be explained. The gate electrode 18, the gate line 15, and the first storage electrode 20 extended from the gate line 15 are formed on the substrate 11. A gate insulating layer 30 is formed on the gate electrode 18, the gate line 15 and the first storage electrode 20.
The TFT “Tr” is formed on the gate insulating layer 30 to be disposed over the gate electrode 18. A passivation layer 55 is formed on the TFT “Tr” and has a drain contact hole 60 that exposes a portion of the drain electrode 46.
A pixel electrode 65 and the second storage electrode 66 extended from the pixel electrode 65 are formed on the passivation layer 55. The pixel electrode 55 may be connected to the drain electrode 46 via the drain contact hole 60. In addition, the second storage electrode 66 is disposed over the first storage electrode 20. The first storage electrode 20 and the second storage electrode 66, with the gate insulating layer 30 and the passivation layer 55 therebetween, are a dielectric configuration that constitutes a storage capacitor “Cst.”
The storage capacitor “Cst” provides a predetermined voltage to the pixel electrode 65 for a predetermined period of time. Accordingly, to maintain the predetermined voltage at the pixel electrode 65 for the predetermined period of time, the storage capacitor “Cst” must have a capacitance “C” that corresponds to the predetermined voltage.
The capacitance “C” of the storage capacitor “Cst” may be depicted as follows:C=∈×A/d  {circle around (1)}
In equation {circle around (1)} above, “C” is capacitance, “∈” is a dielectric constant between first and second storage electrodes, “A” is a size of the first and second electrodes, and “d” is a distance between the first and second electrodes.
According to equation {circle around (1)} above, the capacitance “C” is directly proportional to the size “A” of the first and second storage electrodes and the dielectric constant “∈” between the first and second storage electrodes. The capacitance “C” is also inversely proportional to the distance “d” between the first and second storage electrodes. Thus, the storage capacitor “Cst” may obtain a greater capacitance “C” as the size “A” of the first and second storage electrodes and the dielectric constant “∈” between the first and second storage electrodes increase and the distance “d” between the first and second storage electrodes decrease.
Consequently, because the storage capacitor “Cst” may have a greater capacitor “C” as the size “A” of the storage electrode increases, the gate line 15 having the first storage electrode 20 should have an appropriate width to accommodate the capacitance “C” of the storage capacitor “Cst.”
However, when the width “W1” of the gate line 15 is increased for accommodating an increased capacitance “C,” an aperture ratio of the LCD device is reduced. Thus, the brightness of the LCD device is also reduced.